1. Technical Field
Embodiments of this disclosure relate to semiconductor devices and methods of manufacturing the same and, more particularly, to nonvolatile memory devices having three-dimensional (3-D) structures and methods of manufacturing the same.
2. Related Art
A nonvolatile memory device retains data stored therein although the supply of power is cut off. As the recent improvement of the degree of integration of 2-D memory devices in which memory cells may be formed in a single layer over a silicon substrate reaches the limit, there is proposed a 3-D nonvolatile memory device in which memory cells are vertically stacked in multiple layers from a silicon substrate.
The structure of a known 3-D nonvolatile memory device and problems thereof are described in detail below.
FIG. 1 is a cross-sectional view showing the structure of a known 3-D nonvolatile memory device.
As shown in FIG. 1, the known 3-D nonvolatile memory device includes a channel layer CH vertically protruded from a substrate 10 equipped with a source region ‘source’ and a lower select gate LSG, a plurality of memory cells MC, and the upper select gate USG stacked along the channel layer CH. The plurality of memory cells MC is coupled in series between the lower select gate LSG and the upper select gate USG, thus forming one string. The strings are vertically arranged from the substrate 10.
In FIG. 1, reference numeral ‘11’ denotes an interlayer insulating layer, reference numeral ‘12’ denotes a word line, reference numeral ‘13’ denotes a lower select line, and reference numeral ‘14’ denotes an upper select line. Furthermore, reference numeral ‘15’ denotes a gate insulating layer, and reference numeral ‘16’ collectively denotes a tunnel insulating layer, a memory layer, and a charge blocking layer.
In the known 3-D nonvolatile memory device constructed as above, an N type impurity is doped into the channel layer CH and the source region ‘source’. Accordingly, when an erase operation is performed, the source region ‘source’ generates gate induced drain leakage (GIDL) current and holes generated by the GIDL current are injected into a memory layer.
The known 3-D nonvolatile memory device is problematic in that the erase speed is slow because the number of holes generated by the GIDL current is insufficient and the erase speed is lowered because sufficient holes are not supplied to some of the memory cells. In particular, in the known 3-D nonvolatile memory device, since the strings are vertically arranged from the substrate 10, the supply of holes becomes more difficult as the length of the channel layer CH increases. As a result, the speed of an erase operation is further reduced, and thus the memory device has poor performance.